Content Addressable Memories (CAMs) are special memory devices that allow for rapid location of data based upon a “query pattern”. FIG. 1 shows a prior art embodiment for a Content Addressable Memory (CAM) device. In a CAM, valid data in a storage location 122 of the CAM has associated with it an address 124 in the CAM. In a typical CAM operation, a query pattern is provided to the CAM via an input port 110. This query pattern is latched in a comparand register 120. All storage locations are concurrently accessed from bus 130 and data in each storage location are compared to the value in the comparand 120. If a matched storage location is found, a flag is asserted on the output of the appropriate storage location 140. This, in turn, causes the match port 150 on the CAM to be asserted and the address 124 associated with the matching storage location 122 to be placed on an output bus 160. In certain applications, there are frequently matches to more than one storage location. CAM output selection logic 170 is used to prioritize outputs. In such a multiple match case, the CAM output selection logic 170 can output the appropriate matching address based on a predetermined scheme. If there is no match, then various actions can be taken as appropriate for the host system.
Because of a CAM's inherent ability in conditionally retrieving data, CAM devices are widely used in a number of applications (e.g. networking) where such a feature is needed. However, in many applications, the conditions on which one selects data changes dynamically and frequently, perhaps even in real time. For example, in networking, initially prior to the establishment of a connection between a client and a server, one might access a CAM to route the traffic based on the destination server only (e.g. to a “load balancing” server). However, upon allocation of a particular server to service the connection of the client, it would be desirable to be able to route the traffic based on the attributes, such as network addresses, of the particular server and the client. Thus, there may be a rule for handling traffic to the load-balancing server and a separate rule for handling traffic to the particular server handling a specific connection.
Under conventional CAM usage, typically a network processor is required to re-program the conditions that govern the operation of the CAM for such a condition. With today's data rates of 10 Gigabits, and an average 40 octet datagram, a new datagram arrives every 32 nanoseconds. Thus, every 32 nanoseconds a new datagram will require access to the CAM bus for, as an example, route processing. Allowing access to the CAM bus by the network processor, for the purposes of writing a new rule to handle a specific connection, will likely result in a delay in the processing of a subsequently arriving datagram. The need for the arriving datagram to wait for processing is due to the usage of the CAM bus by the network processor in writing the new rule. While packets may be delayed in processing as described, depending on various factors, the delay may imply that arriving datagrams will be lost if there is no queuing and the arriving datagrams are simply dropped.
Accordingly, an improved CAM without at least some of these disadvantages is desired.